Updated emulator to reflect ISA changes
This commit is contained in:
Kyler
parent
c17585e356
commit
6aff466f4e
103
emulator/main.py
103
emulator/main.py
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@ -1,7 +1,7 @@
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# Kyler Olsen
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# Feb 2024
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MAX_INT = 4089
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MAX_INT = 0x1000
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class Memory:
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@ -94,12 +94,9 @@ class Computer:
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self,
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index: int,
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*,
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top: bool = False,
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strict: bool = False,
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strict: bool = True,
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) -> int:
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if strict and not (0 <= index <= 7): raise IndexError
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elif strict and top and not (0 <= index <= 3): raise IndexError
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elif top and not (0 <= index <= 3): index = (index % 4) + 4
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else: index %= 8
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return self._get_reg(index)
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@ -119,12 +116,9 @@ class Computer:
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index: int,
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value: int,
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*,
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top: bool = False,
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strict: bool = False,
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strict: bool = True,
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):
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if strict and not (0 <= index <= 7): raise IndexError
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elif strict and top and not (0 <= index <= 3): raise IndexError
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elif top and not (0 <= index <= 3): index = (index % 4) + 4
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else: index %= 8
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value %= MAX_INT
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@ -143,6 +137,44 @@ class Computer:
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def interrupt(self, index: int):
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self._interrupt_flag.append(index % MAX_INT)
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def step(self):
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instruction = self._mem[self.program_counter]
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if instruction == 0: self.NOP()
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elif instruction == 1: self.HLT()
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elif instruction == 2: self.INT()
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elif instruction == 3: self.BNZ()
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elif instruction & 0xFF8 == 0x10: self.GET(instruction & 0x7)
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elif instruction & 0xFF8 == 0x18: self.SET(instruction & 0x7)
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elif instruction & 0xFF8 == 0x20: self.LOD(instruction & 0x7)
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elif instruction & 0xFF8 == 0x28: self.STR(instruction & 0x7)
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elif instruction & 0xFF8 == 0x30: self.PSH(instruction & 0x7)
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elif instruction & 0xFF8 == 0x38: self.POP(instruction & 0x7)
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elif instruction & 0xF80 == 0x80: self.LDI(instruction & 0x7F)
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elif instruction & 0xFC0 == 0x100:
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self.LSH(instruction & 0x38, instruction & 0x7)
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elif instruction & 0xFC0 == 0x140:
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self.RSH(instruction & 0x38, instruction & 0x7)
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elif instruction & 0xFC0 == 0x180:
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self.INC(instruction & 0x38, instruction & 0x7)
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elif instruction & 0xFC0 == 0x1C0:
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self.DEC(instruction & 0x38, instruction & 0x7)
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elif instruction & 0xE0 == 0x200:
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self.AND(instruction & 0x1C, instruction & 0x38, instruction & 0x7)
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elif instruction & 0xE0 == 0x400:
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self.OR(instruction & 0x1C, instruction & 0x38, instruction & 0x7)
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elif instruction & 0xE0 == 0x600:
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self.NAD(instruction & 0x1C, instruction & 0x38, instruction & 0x7)
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elif instruction & 0xE0 == 0x800:
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self.SUB(instruction & 0x1C, instruction & 0x38, instruction & 0x7)
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elif instruction & 0xE0 == 0xA00:
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self.XOR(instruction & 0x1C, instruction & 0x38, instruction & 0x7)
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elif instruction & 0xE0 == 0xC00:
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self.NOR(instruction & 0x1C, instruction & 0x38, instruction & 0x7)
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elif instruction & 0xE0 == 0xE00:
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self.ADD(instruction & 0x1C, instruction & 0x38, instruction & 0x7)
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else: raise LookupError()
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# === Operations ===
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def NOP(self):
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@ -156,21 +188,25 @@ class Computer:
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self.interrupt(self.pointer)
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self.program_counter += 1
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def JPZ(self):
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def BNZ(self):
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if self.zero_flag:
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self.program_counter = self.pointer
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self.program_counter += 1
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def GET(self, REG: int):
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self.set_reg(REG, self._interrupt_map[self.pointer])
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self.program_counter += 1
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def SET(self, REG: int):
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self._interrupt_map[self.pointer] = self.get_reg(REG, top=True)
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self._interrupt_map[self.pointer] = self.get_reg(REG)
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self.program_counter += 1
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def LOD(self, REG: int):
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self.set_reg(REG, self._mem[self.pointer], top=True)
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self.set_reg(REG, self._mem[self.pointer])
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self.program_counter += 1
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def STR(self, REG: int):
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self._mem[self.pointer] = self.get_reg(REG, top=True)
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self._mem[self.pointer] = self.get_reg(REG)
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self.program_counter += 1
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def PSH(self, REG: int):
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@ -181,11 +217,15 @@ class Computer:
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self._mem[self.stack_pointer] = self.get_reg(REG)
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self.program_counter += 1
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def LDI(self, Immediate: int):
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self.pointer = Immediate % 0x3F
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self.program_counter += 1
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def LSH(self, REG_D: int, REG_A: int):
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result = self.get_reg(REG_A) << 1
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result %= MAX_INT
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self._zero_flag = result == 0
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self.set_reg(REG_D, result, top=True)
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self.set_reg(REG_D, result)
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self.program_counter += 1
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def RSH(self, REG_D: int, REG_A: int):
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@ -210,28 +250,42 @@ class Computer:
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self.program_counter += 1
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def AND(self, REG_D: int, REG_A: int, REG_B: int):
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result = self.get_reg(REG_A) & self.get_reg(REG_B, top=True)
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result = self.get_reg(REG_A) & self.get_reg(REG_B)
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result %= MAX_INT
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self._zero_flag = result == 0
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self.set_reg(REG_D, result, top=True)
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self.set_reg(REG_D, result)
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self.program_counter += 1
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def XOR(self, REG_D: int, REG_A: int, REG_B: int):
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result = self.get_reg(REG_A) ^ self.get_reg(REG_B, top=True)
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def OR(self, REG_D: int, REG_A: int, REG_B: int):
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result = self.get_reg(REG_A) | self.get_reg(REG_B)
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result %= MAX_INT
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self._zero_flag = result == 0
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self.set_reg(REG_D, result, top=True)
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self.set_reg(REG_D, result)
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self.program_counter += 1
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def NOR(self, REG_D: int, REG_A: int, REG_B: int):
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result = MAX_INT ^ (self.get_reg(REG_A) | self.get_reg(REG_B))
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def NAD(self, REG_D: int, REG_A: int, REG_B: int):
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result = (MAX_INT - 1) ^ (self.get_reg(REG_A) & self.get_reg(REG_B))
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result %= MAX_INT
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self._zero_flag = result == 0
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self.set_reg(REG_D, result)
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self.program_counter += 1
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def SUB(self, REG_D: int, REG_A: int, REG_B: int):
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result = self.get_reg(REG_A) - self.get_reg(REG_B)
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result = self.get_reg(REG_A) + ((MAX_INT - 1) ^ self.get_reg(REG_B)) + 1
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result %= MAX_INT
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self._zero_flag = result == 0
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self.set_reg(REG_D, result)
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self.program_counter += 1
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def XOR(self, REG_D: int, REG_A: int, REG_B: int):
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result = self.get_reg(REG_A) ^ self.get_reg(REG_B)
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result %= MAX_INT
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self._zero_flag = result == 0
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self.set_reg(REG_D, result)
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self.program_counter += 1
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def NOR(self, REG_D: int, REG_A: int, REG_B: int):
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result = (MAX_INT - 1) ^ (self.get_reg(REG_A) | self.get_reg(REG_B))
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result %= MAX_INT
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self._zero_flag = result == 0
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self.set_reg(REG_D, result)
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@ -243,8 +297,3 @@ class Computer:
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self._zero_flag = result == 0
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self.set_reg(REG_D, result)
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self.program_counter += 1
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def LDI(self, REG: int, Immediate: int):
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self.set_reg(REG, Immediate)
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self.program_counter += 1
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